This invention relates, in general, to semiconductor devices, and more particularly, to edge termination structures for such devices.
Traditional power semiconductor devices comprise a PN junction which is created by forming a p-type doped region in an n-type semiconductor substrate. Surrounding the p-type region is a depletion region which is due to the balance of charge between regions of opposite conductivities. In power devices it is important that the breakdown voltage of the PN junction be as high as possible and for breakdown to occur in the bulk substrate, away from the surface of the semiconductor device. To improve the breakdown voltage and the performance of power semiconductor devices, edge termination structures have previously been employed.
One prior method for forming edge termination structures forms concentric floating diffusion rings around the power semiconductor device. Typically a plurality of diffusion rings are formed which are intended to extend the depletion region away from the PN junction at the surface. In order to be effective in high voltage devices, the diffusion rings need to be quite large and deep. Due to the large thermal budget required and, in many cases, the difficulty of process control and reproducibility, these ring structures can be difficult to process and also increase the final die size of the power semiconductor device. This in turn will increase the manufacturing cost of the semiconductor device.
A second prior method for extending the location of the depletion region at the surface of the substrate uses a thick insulator layer. A 1 .mu.m to 2 .mu.m thick layer of insulator material is deposited and patterned near the edge of the PN junction to be protected. A portion of the conductive layer used to connect to the PN junction is then extended over this insulator to create a planar field plate. This will increase the width of the depletion region near the surface and move the edge of the depletion region away from the p-type region at the surface. Although the insulator layer takes up less real estate on a semiconductor substrate, in practice this technique can only provide breakdown voltage enhancement up to 500 volts due to the requirements of the thickness and stress in the insulator materials.
A third prior method for increasing the breakdown voltage of a PN junction forms a resistive region at the surface of the semiconductor substrate near the PN junction. Using an appropriate implant species, lattice damage is created by implanting the surface with a high implant energy. This damaged region increases the surface resistivity of the semiconductor device which in turn extends the depletion region away from the PN junction. This lattice damage, however, will also increase the leakage current of the power semiconductor device which will in turn, degrade other performance characteristics of the device. Such a method also requires accurate control and reproducibility of the lattice defect distribution and adds to the process complexity of the semiconductor device.
By now, it should be appreciated that it would be advantageous to provide an improved method for increasing the breakdown voltage of a PN junction. It would be of further advantage if the breakdown voltage of the device was not dependent on the geometrical contour shape of the PN junction or the surface charge of the substrate, but rather on the doping of the junction regions. It would be of even further advantage if the method could increase the breakdown voltage of a PN junction to beyond 500 volts.